CIS Spring 2002 Meetings

Advisory Committee Meetings and Roundtables
Day One Agenda • May 7th, 2002

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Event	Speaker
Welcome	Prof. Bob Dutton, CIS Director of Research
MOSFET Performance Limits and "New Frontier Devices"	Prof. Dimitri Antoniadis, MIT Slides, Video
Taking FETs to the Limit: Prospects and Challenges	Prof. Tsu-Jae King, U.C. Berkeley Slides, Video
Digital CMOS--Problems and Needs from a High-Performance Perspective	Dr. Tak Ning, IBM, T.J. Watson Research Center Slides, Video
Post Moore's Law Perspective: We need them, not tomorrow, but today	Dr. Kazuo Yano, Hitachi, CRL Slides, Video
Nanowires: Speculation on Integrating Devices and Interconnects	Dr. Ted Kamins, HP Labs, HP Slides, Video
The Realities of System on a Chip	Dr. Hans Stork, Texas Instruments Slides, Video
Single- and Double-Gated FD/SOI for High-Performance Logic	Dr. Zoran Krivokapic, AMD Slides, Video
Challenges in Using Foundry CMOS Processes for Analog/RF Design	Dr. Patrick Yue, Atheros Slides, Video
Building Fast Packet Buffers from Slow Memory	Prof. Nick McKeown, Stanford University Slides, Video
Improving Passive Components and Interconnects in Future Technology	Prof. Simon Wong, Stanford University Slides, Video
Scaling Hurdles--Can Circuit Design Come to the Rescue?	Dr. Ali Keshavarzi, Intel Slides, Video
Integrated Analog/Digital SoC Perspective	Prof. Borivoje Nikolic, U.C. Berkeley Slides, Video
Scaling Issues for Integrated Digital Systems	Prof. Mark Horowitz, Stanford University Slides, Video
Round Table Discussion: "Gaps in 'The Map--'" How are the Scaling Options Matched-up with Circuit/System Needs?	All Presenters Video only (no slides for this session)
Dinner and Talk at Packard Atrium (Due to limited space, dinner is by RSVP only)	Prof. William F. Miller, Computer Science and Graduate School of Business, Stanford University

To Day Two Agenda