In a well-designed front-end circuit for High Energy Physics (HEP), the resolution is limited by the noise from the input stage, and particularly, from the input transistor. In order to increase the resolution, designers of electronics for HEP usually employ a simple noise minimization technique that relies on using maximum power available, minimum length devices, and capacitance matching to achieve lowest noise. Although a good starting point for noise minimization, these simple rules do not always reach an optimum and require further tuning.
In some publications, the minimization problem has been addressed in a more rigorous way, using reasonably accurate noise models and producing results better than those obtained from applying the simple rules previously presented. However, artificial constraints are usually set in the optimization problem in order to reduce the problem complexity. This produces a solution that either yields the optimum size of the input transistor given a certain detector and pulse shaper characteristics, or the optimum pulse shaper design given the amplifier transfer function. An additional problem found when using analytical equations in the design of front-end electronics in HEP arises from the fact that the input MOSFET is usually biased in moderate inversion, leading to model inaccuracies and more a-posteriori fine tuning.
This work presents an accurate design methodology for noise minimization in front-end electronics for HEP. Provided the technology to be used, this methodology tries to reach the global optimal tradeoff curves for power, speed and equivalent noise charge (ENC). To deal with model inaccuracies due to the transistor region of operation, this methodology uses SPICE simulation results as look-up tables for the model parameters, provided that the models are more accurate than simple square-law equations. This technique of gm/Id-based design is extended here to include design for low noise.
The methodology is applied step by step to an actual design -- the ILC detector front-end electronics. A comparison between hand calculations, simulations and silicon results will be presented to show the accuracy of this method. Also some tradeoff curves based on the design methodology will be plotted; these are really useful for a system-level design, to have an idea of how power, speed and noise are traded in the Pareto Optimal curve, and to set reasonable design goals.
Integrated Circuits Lab
Center for Integrated Systems
Stanford University