Integrated Circuits for Broadband Digital Switching

Faculty: Bruce Wooley and Bruce Lusignan
Student: Mehrdad Heshami

The potential capability of new technologies in three fields: fiber optics, protocol standards, and VLSI; fuels the esclating demand for a public broadband telecommunication network, namely BISDN (Broadband Integrated Services Digital Network). Realization of such a widespread network, requires developement of electronic elements that are capable of handling huge amounts of data traffic. These elements should receive, transmit, process and switch digital data with throughputs in the order of giga bits and tera bits per second.

The purpose of this research is to investigate cost effective implementation of broadband digital switches by using available CMOS IC fabrication technology. The emphasis is on the switch elements for networks based on SONET (Synchronous Optical NETwork) and ATM (Asynchronous Transfer Mode) standards. One of the main components of broadband data switches which is usually the speed bottle neck of the switching system is the data buffer. Therefore, the design of a high throughput memory for use as a data buffer is a major part of this research. High performance circuit pipelining technique as a means to achieve high throughput, is investigated and clocking schemes to improve the pipeline performance are proposed.

A prototype pipelined dynamic memory using three transistor memory cell has been designed, fabricated and tested as a high throughput data buffer. Hamming error correction coding (ECC) is used to enhance the memory's immunity to soft errors, as well as improve its fabrication yield. A high performance pipelining technique, called `skewed-clock pipelining' is used to achieve operating frequency of up to 250 MHz using a conventional 0.8u CMOS process.

Papers

M. Heshami, B.A. Wooley, "A 250 MHz skewed-clock pipelined dual-port embedded DRAM", IEEE Custom Integrated Circuit Conference, May 1995.
M. Heshami, B.A. Wooley, "A 250 MHz skewed-clock pipelined dual-port embedded DRAM", to be published in the IEEE Journal of Solid State Circuits.

Resume

Mehrdad Hesahmi received the B.S. degree in electronics engineering from Sharif University of Technology, Tehran, Iran in 1989 and the M.S. degree in electrical engineering from Stanford University, Stanford, CA in 1992. He is currently a Ph.D. candidate in electrical engineering at Stanford University. During the summer of 1991 he worked at Chrontel Inc., Milpitas, CA, where he designed a RAMDAC chip. Over the summer of 1992 he was employed at Hewlett Packard Co. where he participated in the design of a high speed SRAM. During summer of 1994 he designed a phase locked loop at Rockwell International Co., Newport Beach, CA. His research interests are in the area of high performance analog, digital and mixed-mode circuit design.

email: heshami@hpl.hp.com

Stanford University
Center for Integrated Systems
Integrated Circuits Lab