Conventional sigma-delta ADC has been widely used for low to medium bandwidth with high resolution applications such as audio signal processing. In these applications, the oversampling ratio of sigma-delta modulator was very high up to 1024. However, recent demand for wideband communication stimulates the interest for wider bandwidth sigma-delta modulator. With these requirements, the oversampling ratio was lowered below 32. To compensate for the performance loss due to the lower oversampling ratio, higher order modulator or multibit quantization were actively employed.
In switched capacitor domain, the performance of sigma-delta modulator was mainly limited by the performance of operational amplifiers used in active integrators. Especially, under low oversampling ratio environment, this performance requirement of operational amplifier becomes more stringent. Moreover, in deep-submicron technology, the design of high performance operational amplifier faces more challenges.
The objective of this research is to develop high speed sigma-delta ADC (several MHz signal bandwidth) with more than 14 bits of resolution under low voltage operation less than 1.5V. The method to reduce the number as well as relax the performance requirement of operational amplifiers, architectural variations for aggressive noise shaping, DAC linearization method and circuit level approaches for wideband low voltage operation will be explored.
Integrated Circuits Lab
Center for Integrated Systems
Stanford University