The scaling of CMOS technology is enabling ubiquitous mobile digital computing environment. In order to provide more functionality and speed in a smaller form factor, considerable effort has been focused on continuing the scaling of CMOS device. However, the aggressive technology scaling mandates reduced power supply for device reliability. Moreover, reduced power consumption requirements for mobility is another driving force for the lower supply voltage. Another constraint associated with CMOS device scaling is reduced intrinsic gain of MOS transistors.
Supply voltage reduction and decreased transistor intrinsic gain impose significant challenges on analog-to-digital interface design, one of the most critical mixed-signal function blocks. The lower supply voltage reduces available signal swing typically increasing the analog power dissipation needed to achieve a given dynamic range (DR). Moreover, reduced supply voltage restricts the choice of circuit topologies due to the limited voltage headroom. Reduced transistor intrinsic gain further complicates building high-precision analog circuits. The objective of this research has been to investigate the methods for realization of high-precision CMOS analog-to-digital converters in a sub-1V environment without compromising power efficiency.
In this research, a low-voltage low-power sigma-delta modulator with digital-audio performance is introduced. To accommodate a 0.7-V power supply with relaxed analog component constraints, input feedforward with tracking multi-bit quantization is employed. In order to achieve high precision with robust operation, a single comparator tracking multi-bit quantization approach is proposed. The resulting increased modulator feedback timing overhead is overcome with a delayed input feedforward approach. For flicker noise reduction, chopper stabilization is used in the first stage operational amplifier. To further reduce analog power dissipation, the incomplete but linear settling behavior of the first stage is explored. Low-voltage circuit techniques such as locally bootstrapped or boosted switches are also employed.
An experimental prototype of the proposed modulator has been integrated in a 0.18-um CMOS technology. The prototype achieves 100 dB of DR, 100-dB peak signal-to-noise ratio (SNR) and 95-dB peak signal-to-noise-and-distortion ratio (SNDR) for a signal bandwidth of 25 kHz while consuming only 870-uW of total power from a 0.7-V power supply at a 5-MHz sampling rate.
Integrated Circuits Lab
Center for Integrated Systems
Stanford University