The fastest A/D converters use either a flash or folding and interpolating circuit architecture. CMOS flash converters can provide between 4 to 8 bits of resolution with sampling rates as high as 1.5 GSa/sec, but require a large amount of power and area. Folding and Interpolating converters use analog pre-processing circuits to reduce the number of comparators required relative to a flash converter; however, the bandwidth of the analog pre-processing often limits the sampling rate. Today's CMOS folding and interpolating converters provide about 6 bits of resolution at about 500 MSa/s.
As CMOS technology scales to smaller dimensions, the design of ever faster A/D converters is complicated by both increases in device mismatch and reductions in supply voltage. Obtaining even 4 to 6 bits of resolution in submicron CMOS often requires some form of digital or analog calibration. Part of this research will involve investigating trade-offs between circuit area and power for various calibration/trimming techniques as well as offset averaging methods.
Integrated
Circuits Lab
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