Research supported by The Fannie and John Hertz Foundation and National Semiconductor Corporation
The increasing cost effectiveness of digital implementations of signal processing and communication functions has led to an increasing level of attention devoted to the problems associated with analog to digital and digital to analog conversion circuits. The accuracy obtainable by signal processing systems is frequently limited by the accuracy of the data conversion circuits which interface analog signals to the digital circuits where the processing is performed. Manufacturers of data converter integrated circuits (ICs) are thus continually striving to produce data converters with a high level of accuracy despite the constraints imposed by the IC fabrication process. In particular, random variations in the parameters of integrated devices cause variations in the transfer characteristics of data converters which can reduce their accuracy. This research project addresses two complementary methods commonly used to reduce the effects of device parameter variations: linearity testing and digital error correction. Although the techniques developed in this project specifically pertain to Nyquist rate analog to digital converters, some of the same principles can also be applied in the case of oversampling converters and digital to analog converters.
Linearity testing ameliorates the effects of device parameter variations by discarding or downgrading a subset of converter ICs after they are fabricated so that those remaining are guaranteed to meet a set of accuracy specifications. Economic constraints limit the amount of time that can be allocated to the measurements on which the pass/fail decisions are based, so that efficient measurement methods are required to maintain a high level of accuracy. In the present project, a statistical framework is developed in which the effectiveness of measurement methods can be evaluated. Within this framework, the presently available methods are analyzed and several more effective new methods are suggested.
While linearity testing procedures ensure that a high level of accuracy is maintained in data converter ICs, they do so at the expense of discarding a fraction of the ICs that are fabricated, thus increasing the cost of each deliverable device. Digital error correction is a method that can be employed at the design stage to reduce the sensitivity of the data converter transfer characteristics to device parameter variations. By implementing a model of the most significant effects of device parameter variations in digital circuitry, a digital correction signal can be generated. The most sig- nificant effects can then be removed by adding the correction signal to the output of the A/D converter. The primary economic constraint on error correction systems is the integrated circuit area required for the implementation of the digital circuitry. The statistical framework developed to evaluate linearity test methods can be used again in the case of error correction methods, both to evaluate the efficiency of presently available methods and to devise more effective new methods.
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