The continuing scaling of CMOS VLSI technology, together with the demands for increased bandwidth and resolution in broadband data communication systems, imposes increasingly severe constraints on interfaces between the digital and analog representations of information. As consequence, these interfaces often account for a disproportionate share of the power dissipation in communications transceivers that make extensive use of digital signal processing to implement the emerging protocols for local and wide area communications. It is the objective of this research to explore new approaches to implementing such interfaces in order to achieve substantial savings in power while accommodating the supply voltage, and thus dynamic range, constraints imposed by the scaling of CMOS technology. Specifically, we are exploring novel oversampling architectures for digital-to-analog conversion in which the out-of-band quantization noise can be suppressed and the linearity and timing accuracy requirements for the D/A interface can be relaxed.
In the architecture we are exploring, an analog quasi-sigma-delta modulator is merged with the digital noise-shaping modulator so as to construct a closed-loop noise shaping digital-to-analog converter. There are two D/A interfaces between the digital and analog modulators. The single-bit output signal of the digital modulator is converted into the analog domain by an inherently linear two-level D/A interface. The quantization error of the digital modulator is first quantized into an n-bit code and then converted into an analog signal to form a second input to the analog modulator. In this way it appears possible to embed the digital-to-analog interface, the discrete-time to continuous time conversion, and the reconstruction filtering in the forward path of a feedback system. As a result, the linearity and timing accuracy required of the D-to-A interface are relaxed and the out-of-band quantization noise suppressed.
An evaluation of the use of a hybrid cascade of digital and analog noise shaping modulators to relax the D/A interface requirements and suppress both in-band and out-of-band quantization noise in oversampling D/A converters has been made. Several hybrid architectures with difference design choices have been evaluated and compared through system level simulations. The transistor-level architectures are currently being investigated. Practical issues and non-idealities will be investigated further and taken into account in the circuit design.
Integrated Circuits Lab