High-speed, High-resolution Digital-to-Analog Converters

Faculty: Bruce Wooley

Student: Katy Falakshahi

Some Retro Intro

Ladies and Gentlemen, let's face it. The advances in integrated circuit processing leads to faster, more complicated digital chips. And of course digital signal processing is more immune to noise and non_linearity than their analog counterparts. So what's the natural outcome? Larger and larger portions of systems are digitized. However, we, humans, are the ultimate users of all systems, and our 5-6 senses are analog by design. Therefore, no matter how advanced the digital signal processing and digital IC processes become, the smart designers (who care enough about the marketing aspect of their designs to make it user-friendly) would need to put some kind of analog/digital interface in the system.

If the predictions of the great Nostradamus are correct, in about 1021 years after the massacre of huns by the Tatars, (about 10 years from now), analog to digital and digital to analog converter designers will be the rulers of the world of IC design. No matter how fast and accurate the digital portion of the chip is, the digital designers should wait in agony and fear to see how fast the interface is (which is always slower and less accurate than the DSP portion). But who dictates the overall speed/performance/accuracy? The mighty interface designer.

By now, you should all have guessed what topic I picked for my research: high velocity (oops, I meant speed), high resolution digital to analog (D/A) converters. And while I was waiting for my chip to be fabricated (which took more than twice the usual) I started reading the great Machiavellian books, to get ready to rule the world. Now, my chip is back and tested, and victory shall be mine!

Now the serious portion of the web page:

I decided to use an oversampled digital modulator (sigma-delta) to achieve 14 bits at 5 MHz signal badwidth. A digital sigma-delta modulator consists of adders and delay elements. For high clock rates, the speed of the modulator will be limited by the speed of the adders (in this design, 18 bit adders). We decided to use pipelining to alleviate this speed limit. Furthermore, by choosing the feedback coefficients of the modulators mostly factors of two, and adding extra delay elements to the traditional design, we managed to come up with a highly modular architecture.

We chose a multi-bit digital modulator, and used Philips' current calibration technique to overcome the nonlinearity inherent in multi-bit designs. The current calibration is an elegant, classic approach, and I highly recommend you to read the Philips paper to boost up your spirit on your bad hair days.

Finally, I made my chip, and it took forever to come back (literally). I will keep you all posted on the outcome! You are all more than welcome to light candles and pray for my dear chips to outperform my wildest dreams. I really appreciate your time and consideration.

PUBLICATIONS

Hema Dhanesha, Mark Horowitz and Katayoun Falakshahi, "Array-of-Arrays Architecture for Parallel Floating Point Multiplication," 1995 Conference on Advanced Research in VLSI, Chapel Hill, NC.

K. Falakshahi, C.-K. K. Yang, and Bruce A. Wooley,"A 14-bit, 5-MHz Digital-to-Analog Converter Using Multi-bit Sigma-Delta Modulation," Sym. on VLSI Circuits Digest of Technical Papers, pp164-165, June 1998.

K. Falakshahi, C.-K. K. Yang, and Bruce A. Wooley,"A 14-bit, 10-Msamples/sec Digital-to-Analog Converter Using Multi-bit Sigma-Delta Modulation," Invited for JSSC special edition on VLSI circuits symposium, April 1999.

PRESENTATIONS

Katy Falakshahi, "High-speed, High-Resolution D/A Conversion in CMOS," Ph.D. defense slides, August 1998.

KNOWLEDGE MANAGEMENT
Link to the group resource page

CONTACT
Center for Integrated Systems, #067
Stanford University
Stanford, CA 94305
voice: (650) 725-4543
fax: (650) 725-3383

Email: katayoun@par.Stanford.EDU

Integrated Circuits Lab